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ADE7566/ADE7569
Table 37. Interrupt Status Register 2 SFR (MIRQSTM, 0xDD)
Preliminary Technical Data
Bit No.
7
6
5
4
3
2
1
0
Interrupt Flag
CF2
CF1
VAEOF
REOF 1
AEOF
VAEHF
REHF 1
AEHF
Description
Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if CF2 pulse output is not enabled by
clearing Bit 2 of MODE1 register.
Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if CF1 pulse output is not enabled by
clearing Bit 1 of MODE1 register.
Logic 1 indicates that the VAHR register has overflowed.
Logic 1 indicates that the VARHR register has overflowed.
Logic 1 indicates that the WATTHR register has overflowed.
Logic 1 indicates that the VAHR register is half-full.
Logic 1 indicates that the VARHR register is half-full.
Logic 1 indicates that the WATTHR register is half-full.
1
This function is not available in the ADE7566 part.
Table 38. Interrupt Status Register 3 SFR (MIRQSTH, 0xDE)
Bit No.
7
6
5
4
3
2
1
0
Interrupt Flag
RESET
–
WFSM
PKI
PKV
CYCEND
ZXTO
ZX
Description
Indicates the end of a reset (for both software and hardware reset).
Reserved.
Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7).
Logic 1 indicates that current channel has exceeded the IPKLVL value
Logic 1 indicates that voltage channel has exceeded the VPKLVL value.
Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles.
Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles.
Logic 1 indicates detection of a zero crossing in the voltage channel.
Table 39. Interrupt Enable Register 1 SFR (MIRQENL, 0xD9)
Bit No.
7 to 5
4
3
2
1
0
Interrupt Enable Bit
Reserved
VARSIGN 1
APSIGN
VANOLOAD
RNOLOAD 1
APNOLOAD
Description
Reserved.
When set, the VARSIGN bit set creates a pending ADE interrupt to the 8052 core.
When set, the APSIGN bit set creates a pending ADE interrupt to the 8052 core.
When set, the VANOLOAD bit set creates a pending ADE interrupt to the 8052 core.
When set, the RNOLOAD bit set creates a pending ADE interrupt to the 8052 core.
When set, the APNOLOAD bit set creates a pending ADE interrupt to the 8052 core.
1
This function is not available in the ADE7566 part.
Table 40. Interrupt Enable Register 2 SFR (MIRQENM, 0xDA)
Bit No.
7
6
5
4
3
2
1
0
Interrupt Enable Bit
CF2
CF1
VAEOF
REOF 1
AEOF
VAEHF
REHF 1
AEHF
Description
When this bit is set, a CF2 pulse creates a pending ADE interrupt to the 8052 core.
When this bit is set, a CF1 pulse creates a pending ADE interrupt to the 8052 core.
When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
1
This function is not available in the ADE7566 part.
Rev. PrA | Page 40 of 136
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